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Placement methodology to remove filler |
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Integrated circuits (ICs) employing additional output vertical interconnect access(es) (VIA(s)) coupled to a circuit output VIA to decrease circuit output resistance |
Haining Yang, John Jianhong Zhu |
2019-11-19 |
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Integrated circuit (IC) employing a channel structure layout having an active semiconductor channel structure(s) and an isolated neighboring dummy semiconductor channel structure(s) for increased uniformity |
Haining Yang |
2019-10-01 |
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Multiple via structure for high performance standard cells |
Satyanarayana Sahu, Venugopal Boynapalli, Hyeokjin Lim, Mickael Malabry, Mukul Gupta |
2019-03-19 |
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Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance |
Haining Yang |
2019-02-05 |
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Hybrid coloring methodology for multi-pattern technology |
Hyeokjin Lim, Ohsang Kwon, Mickael Malabry, Jingwei Zhang, Raymond George Stephany +5 more |
2019-01-08 |