Issued Patents 2019
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10497702 | Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells | Da Yang, Jeffrey Junhao Xu | 2019-12-03 |
| 10483200 | Integrated circuits (ICs) employing additional output vertical interconnect access(es) (VIA(s)) coupled to a circuit output VIA to decrease circuit output resistance | Haining Yang, Xiangdong Chen | 2019-11-19 |
| 10354912 | Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs) | Jeffrey Junhao Xu, Choh Fei Yeap | 2019-07-16 |
| 10283526 | Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop | Jeffrey Junhao Xu, Mustafa Badaroglu | 2019-05-07 |