Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10510872 | FinFETs and methods for forming the same | — | 2019-12-17 |
| 10504840 | Reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC) | — | 2019-12-10 |
| 10497625 | Method and apparatus of multi threshold voltage CMOS | Choh Fei Yeap | 2019-12-03 |
| 10497702 | Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells | John Jianhong Zhu, Da Yang | 2019-12-03 |
| 10439039 | Integrated circuits including a FinFET and a nanostructure FET | Stanley Seungchul Song, Kern Rim, Choh Fei Yeap | 2019-10-08 |
| 10374063 | FinFETs and methods for forming the same | — | 2019-08-06 |
| 10354912 | Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs) | John Jianhong Zhu, Choh Fei Yeap | 2019-07-16 |
| 10347579 | Reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC) | — | 2019-07-09 |
| 10283526 | Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop | John Jianhong Zhu, Mustafa Badaroglu | 2019-05-07 |