Issued Patents 2019
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10318689 | Integrated circuit logic extraction using cloning and expansion for engineering change order | George Antony, Ankit N. Kagliwal, Vinay K. Singh | 2019-06-11 |
| 10223491 | Integrated circuit design changes using through-silicon vias | Harry Barowski, Joachim Keinert, Haoxing Ren, Sourav Saha | 2019-03-05 |
| 10216885 | Adjusting scan connections based on scan control locations | Raghu G. GopalaKrishnaSetty, Ankit N. Kagliwal, James D. Warnock | 2019-02-26 |
| 10168386 | Scan chain latency reduction | George Antony, Mary P. Kusko, Shrinivas Shenoy | 2019-01-01 |