Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10417366 | Layout of large block synthesis blocks in integrated circuits | Harry Barowski, Harald D. Folberth, Joachim Keinert | 2019-09-17 |
| 10366191 | Layout of large block synthesis blocks in integrated circuits | Harry Barowski, Harald D. Folberth, Joachim Keinert | 2019-07-30 |
| 10242140 | Layout of large block synthesis blocks in integrated circuits | Harry Barowski, Harald D. Folberth, Joachim Keinert | 2019-03-26 |
| 10235487 | Layout of large block synthesis blocks in integrated circuits | Harry Barowski, Harald D. Folberth, Joachim Keinert | 2019-03-19 |
| 10229238 | Congestion aware layer promotion | Christopher J. Berry, Lakshmi N. Reddy | 2019-03-12 |
| 10223491 | Integrated circuit design changes using through-silicon vias | Harry Barowski, Joachim Keinert, Sridhar H. Rangarajan, Haoxing Ren | 2019-03-05 |
| 10223489 | Placement clustering-based white space reservation | Harry Barowski, Ajith Kumar M. Chandrasekaran, Harald D. Folberth, Joachim Keinert | 2019-03-05 |
| 10169519 | Area sharing between multiple large block synthesis (LBS) blocks | Harry Barowski, Harald D. Folberth, Joachim Keinert | 2019-01-01 |
| 10169523 | Timing constraints formulation for highly replicated design modules | Chithra Ravindranath, Rajashree Srinidhi | 2019-01-01 |