Issued Patents 2019
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10417366 | Layout of large block synthesis blocks in integrated circuits | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2019-09-17 |
| 10367481 | Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature | Werner Juchmes, Michael Kugel, Wolfgang Penth | 2019-07-30 |
| 10366191 | Layout of large block synthesis blocks in integrated circuits | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2019-07-30 |
| 10333508 | Cross bar switch structure for highly congested environments | Kurt Lind, Friedrich Schroeder | 2019-06-25 |
| 10242140 | Layout of large block synthesis blocks in integrated circuits | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2019-03-26 |
| 10235487 | Layout of large block synthesis blocks in integrated circuits | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2019-03-19 |
| 10223491 | Integrated circuit design changes using through-silicon vias | Joachim Keinert, Sridhar H. Rangarajan, Haoxing Ren, Sourav Saha | 2019-03-05 |
| 10223489 | Placement clustering-based white space reservation | Ajith Kumar M. Chandrasekaran, Harald D. Folberth, Joachim Keinert, Sourav Saha | 2019-03-05 |
| 10169519 | Area sharing between multiple large block synthesis (LBS) blocks | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2019-01-01 |
| 10170199 | Testing content addressable memory and random access memory | Sheldon B. Levenstein, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter | 2019-01-01 |