Issued Patents 2019
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10502782 | Synthesis for random testability using unreachable states in integrated circuits | Victor N. Kravets, Haoxing Ren, Spencer K. Millican | 2019-12-10 |
| 10386912 | Operating pulsed latches on a variable power supply | Steven M. Douskey, Raghu G. GopalaKrishnaSetty, Hari Krishnan Rajeev, James D. Warnock | 2019-08-20 |
| 10379159 | Minimization of over-masking in an on product multiple input signature register (OPMISR) | Steven M. Douskey, Michael J. Hamilton, Amanda R. Kaufer, Matthew B. Schallhorn | 2019-08-13 |
| 10371747 | Physically aware scan diagnostic logic and power saving circuit insertion | William V. Huott, Ankit N. Kagliwal, Robert C. Redburn | 2019-08-06 |
| 10371749 | Removal of over-masking in an on product multiple input signature register (OPMISR) test | Steven M. Douskey, Amanda R. Kaufer, Michael J. Hamilton, Matthew B. Schallhorn | 2019-08-06 |
| 10371750 | Minimization of over-masking in an on product multiple input signature register (OPMISR) | Steven M. Douskey, Matthew B. Schallhorn | 2019-08-06 |
| 10345380 | Implementing over-masking removal in an on product multiple input signature register (OPMISR) test due to common channel mask scan registers (CMSR) loading | Steven M. Douskey, Matthew B. Schallhorn, Amanda R. Kaufer, Michael J. Hamilton | 2019-07-09 |
| 10254336 | Iterative N-detect based logic diagnostic technique | Gary W. Maier, Franco Motika, Phong T. Tran | 2019-04-09 |
| 10247776 | Structurally assisted functional test and diagnostics for integrated circuits | Franco Motika, Gerard M. Salem | 2019-04-02 |
| 10169510 | Dynamic fault model generation for diagnostics simulation and pattern generation | Gary W. Maier, Franco Motika, Phong T. Tran | 2019-01-01 |
| 10168386 | Scan chain latency reduction | George Antony, Sridhar H. Rangarajan, Shrinivas Shenoy | 2019-01-01 |