Issued Patents 2019
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10437729 | Non-disruptive clearing of varying address ranges from cache | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael A. Blake, Pak-kin Mak, Guy G. Tracy +1 more | 2019-10-08 |
| 10402328 | Configuration based cache coherency protocol selection | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael Fee, Arthur J. O'Neill | 2019-09-03 |
| 10394712 | Configuration based cache coherency protocol selection | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael Fee, Arthur J. O'Neill | 2019-08-27 |
| 10380020 | Achieving high bandwidth on ordered direct memory access write stream into a processor cache | Ekaterina M. Ambroladze, Timothy C. Bronson, Matthias Klein, Pak-kin Mak, Vesselina K. Papazova +1 more | 2019-08-13 |
| 10379776 | Operation interlocking in an address-sliced cache system | Deanna Postles Dunn Berger, Michael A. Blake, Ashraf ElSharif, Kenneth D. Klapproth, Pak-kin Mak +1 more | 2019-08-13 |
| 10331576 | Deadlock avoidance in a multi-processor computer system with extended cache line locking | Michael A. Blake, Pak-kin Mak, Timothy W. Steele, Gary E. Strait, Poornima P Sulibele +1 more | 2019-06-25 |
| 10310982 | Target cache line arbitration within a processor cluster | Deanna Postles Dunn Berger, Johnathon J. Hoste, Pak-kin Mak, Arthur J. O'Neill | 2019-06-04 |