Issued Patents 2019
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10437729 | Non-disruptive clearing of varying address ranges from cache | Deanna Postles Dunn Berger, Michael A. Blake, Pak-kin Mak, Robert J. Sonnelitter, III, Guy G. Tracy +1 more | 2019-10-08 |
| 10402328 | Configuration based cache coherency protocol selection | Deanna Postles Dunn Berger, Michael Fee, Arthur J. O'Neill, Robert J. Sonnelitter, III | 2019-09-03 |
| 10394712 | Configuration based cache coherency protocol selection | Deanna Postles Dunn Berger, Michael Fee, Arthur J. O'Neill, Robert J. Sonnelitter, III | 2019-08-27 |
| 10380020 | Achieving high bandwidth on ordered direct memory access write stream into a processor cache | Timothy C. Bronson, Matthias Klein, Pak-kin Mak, Vesselina K. Papazova, Robert J. Sonnelitter, III +1 more | 2019-08-13 |
| 10169260 | Multiprocessor cache buffer management | Deanna Postles Dunn Berger, Michael Fee, Arthur J. O'Neill | 2019-01-01 |
| 10169272 | Data processing apparatus and method | Norbert Hagspiel, Sascha Junghans, Matthias Klein, Jeorg Walter | 2019-01-01 |