Issued Patents 2019
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10402328 | Configuration based cache coherency protocol selection | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael Fee, Robert J. Sonnelitter, III | 2019-09-03 |
| 10394712 | Configuration based cache coherency protocol selection | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael Fee, Robert J. Sonnelitter, III | 2019-08-27 |
| 10310982 | Target cache line arbitration within a processor cluster | Deanna Postles Dunn Berger, Johnathon J. Hoste, Pak-kin Mak, Robert J. Sonnelitter, III | 2019-06-04 |
| 10169260 | Multiprocessor cache buffer management | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael Fee | 2019-01-01 |