YW

Yishan Wang

CS Cadence Design Systems: 3 patents #23 of 394Top 6%
Overall (2019): #61,962 of 560,194Top 15%
3
Patents 2019

Issued Patents 2019

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
10303828 Integrated circuit simulation with efficient memory usage Jaideep Mukherjee, Saibal Saha, Jianyu Li, Walter J. Ghijsen 2019-05-28
10248745 Integrated circuit simulation with variability analysis for efficient memory usage Jaideep Mukherjee, Saibal Saha, Jianyu Li, Walter J. Ghijsen 2019-04-02
10248747 Integrated circuit simulation with data persistency for efficient memory usage Jaideep Mukherjee, Saibal Saha, Jianyu Li, Walter J. Ghijsen 2019-04-02