JM

Jaideep Mukherjee

CS Cadence Design Systems: 3 patents #23 of 394Top 6%
📍 San Jose, CA: #1,072 of 6,652 inventorsTop 20%
🗺 California: #9,221 of 67,890 inventorsTop 15%
Overall (2019): #86,336 of 560,194Top 20%
3
Patents 2019

Issued Patents 2019

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
10303828 Integrated circuit simulation with efficient memory usage Saibal Saha, Jianyu Li, Yishan Wang, Walter J. Ghijsen 2019-05-28
10248745 Integrated circuit simulation with variability analysis for efficient memory usage Saibal Saha, Jianyu Li, Yishan Wang, Walter J. Ghijsen 2019-04-02
10248747 Integrated circuit simulation with data persistency for efficient memory usage Saibal Saha, Jianyu Li, Yishan Wang, Walter J. Ghijsen 2019-04-02