Issued Patents 2018
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10141936 | Pipelined interconnect circuitry with double data rate interconnections | David Lewis, Carl Ebeling | 2018-11-27 |
| 10055526 | Regional design-dependent voltage control and clocking | David Lewis | 2018-08-21 |
| 10044344 | Systems and methods for a low hold-time sequential input stage | Dana How | 2018-08-07 |
| 9946826 | Circuit design implementations in secure partitions of an integrated circuit | Sean R. Atsatt, Ting Lu, Dana How | 2018-04-17 |
| 9922157 | Sector-based clock routing methods and apparatus | Carl Ebeling, Dana How, Mahesh A. Iyer, Saurabh Adya | 2018-03-20 |