| 10146543 |
Conversion system for a processor with an expandable instruction set architecture for dynamically configuring execution resources |
G. Glenn Henry, Rodney E. Hooker, Douglas R. Reed |
2018-12-04 |
| 10127041 |
Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources |
G. Glenn Henry, Rodney E. Hooker, Douglas R. Reed |
2018-11-13 |
| 10108431 |
Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep state |
G. Glenn Henry, Brent Bean, Stephan Gaskins |
2018-10-23 |
| 10019260 |
Fingerprint units comparing stored static fingerprints with dynamically generated fingerprints and reconfiguring processor settings upon a fingerprint match |
G. Glenn Henry, Rodney E. Hooker, Colin Eddy |
2018-07-10 |
| 9972375 |
Sanitize-aware DRAM controller |
Rodney E. Hooker, Douglas R. Reed |
2018-05-15 |
| 9967092 |
Key expansion logic using decryption key primitives |
G. Glenn Henry, Brent Bean, Thomas A. Crispin |
2018-05-08 |
| 9952654 |
Centralized synchronization mechanism for a multi-core processor |
G. Glenn Henry |
2018-04-24 |
| 9911008 |
Microprocessor with on-the-fly switching of decryption keys |
G. Glenn Henry, Brent Bean, Thomas A. Crispin |
2018-03-06 |
| 9898303 |
Multi-core hardware semaphore in non-architectural address space |
G. Glenn Henry |
2018-02-20 |
| 9898291 |
Microprocessor with arm and X86 instruction length decoders |
G. Glenn Henry, Rodney E. Hooker |
2018-02-20 |
| 9891918 |
Fractional use of prediction history storage for operating system routines |
Rodney E. Hooker, John Bunda |
2018-02-13 |
| 9892283 |
Decryption of encrypted instructions using keys selected on basis of instruction fetch address |
G. Glenn Henry, Brent Bean, Thomas A. Crispin |
2018-02-13 |
| 9891927 |
Inter-core communication via uncore RAM |
G. Glenn Henry, Rodney E. Hooker, Stephan Gaskins |
2018-02-13 |