Issued Patents 2018
Showing 1–25 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10146547 | Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor | Gerard M. Col, Colin Eddy | 2018-12-04 |
| 10146546 | Load replay precluding mechanism | Gerard M. Col, Colin Eddy | 2018-12-04 |
| 10146543 | Conversion system for a processor with an expandable instruction set architecture for dynamically configuring execution resources | Rodney E. Hooker, Terry Parks, Douglas R. Reed | 2018-12-04 |
| 10146540 | Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor | Gerard M. Col, Colin Eddy | 2018-12-04 |
| 10146539 | Load replay precluding mechanism | Gerard M. Col, Colin Eddy | 2018-12-04 |
| 10140574 | Neural network unit with segmentable array width rotator and re-shapeable weight memory to match segment width to provide common weights to multiple rotator segments | Kim C. Houck, Parviz Palangpour | 2018-11-27 |
| 10133580 | Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor | Gerard M. Col, Colin Eddy | 2018-11-20 |
| 10133579 | Mechanism to preclude uncacheable-dependent load replays in out-of-order processor | Gerard M. Col, Colin Eddy | 2018-11-20 |
| 10126793 | Method of managing power consumption within a multi-core microprocessor utilizing an inter-core state discovery process to identify a least power-conserving target core state of all of the cores that share the resource | Darius D. Gaskins | 2018-11-13 |
| 10127046 | Mechanism to preclude uncacheable-dependent load replays in out-of-order processor | Gerard M. Col, Colin Eddy | 2018-11-13 |
| 10127041 | Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources | Rodney E. Hooker, Terry Parks, Douglas R. Reed | 2018-11-13 |
| 10120689 | Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor | Gerard M. Col, Colin Eddy | 2018-11-06 |
| 10114794 | Programmable load replay precluding mechanism | Gerard M. Col, Colin Eddy | 2018-10-30 |
| 10114646 | Programmable load replay precluding mechanism | Gerard M. Col, Colin Eddy | 2018-10-30 |
| 10108430 | Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor | Gerard M. Col, Colin Eddy | 2018-10-23 |
| 10108420 | Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor | Gerard M. Col, Colin Eddy | 2018-10-23 |
| 10108421 | Mechanism to preclude shared ram-dependent load replays in an out-of-order processor | Gerard M. Col, Colin Eddy | 2018-10-23 |
| 10108427 | Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor | Gerard M. Col, Colin Eddy | 2018-10-23 |
| 10108428 | Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor | Gerard M. Col, Colin Eddy | 2018-10-23 |
| 10108429 | Mechanism to preclude shared RAM-dependent load replays in an out-of-order processor | Gerard M. Col, Colin Eddy | 2018-10-23 |
| 10108431 | Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep state | Terry Parks, Brent Bean, Stephan Gaskins | 2018-10-23 |
| 10095514 | Mechanism to preclude I/O-dependent load replays in an out-of-order processor | Gerard M. Col, Colin Eddy | 2018-10-09 |
| 10095868 | Event-based apparatus and method for securing bios in a trusted computing system during execution | — | 2018-10-09 |
| 10089470 | Event-based apparatus and method for securing BIOS in a trusted computing system during execution | — | 2018-10-02 |
| 10089112 | Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor | Gerard M. Col, Colin Eddy | 2018-10-02 |