Issued Patents 2018
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10146539 | Load replay precluding mechanism | Gerard M. Col, G. Glenn Henry | 2018-12-04 |
| 10146546 | Load replay precluding mechanism | Gerard M. Col, G. Glenn Henry | 2018-12-04 |
| 10146540 | Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-12-04 |
| 10146547 | Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-12-04 |
| 10133580 | Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-11-20 |
| 10133579 | Mechanism to preclude uncacheable-dependent load replays in out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-11-20 |
| 10127046 | Mechanism to preclude uncacheable-dependent load replays in out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-11-13 |
| 10120689 | Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-11-06 |
| 10114794 | Programmable load replay precluding mechanism | Gerard M. Col, G. Glenn Henry | 2018-10-30 |
| 10114646 | Programmable load replay precluding mechanism | Gerard M. Col, G. Glenn Henry | 2018-10-30 |
| 10108428 | Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-10-23 |
| 10108420 | Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-10-23 |
| 10108421 | Mechanism to preclude shared ram-dependent load replays in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-10-23 |
| 10108427 | Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-10-23 |
| 10108429 | Mechanism to preclude shared RAM-dependent load replays in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-10-23 |
| 10108430 | Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-10-23 |
| 10095514 | Mechanism to preclude I/O-dependent load replays in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-10-09 |
| 10089112 | Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-10-02 |
| 10088881 | Mechanism to preclude I/O-dependent load replays in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-10-02 |
| 10083038 | Mechanism to preclude load replays dependent on page walks in an out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-09-25 |
| 10019260 | Fingerprint units comparing stored static fingerprints with dynamically generated fingerprints and reconfiguring processor settings upon a fingerprint match | G. Glenn Henry, Rodney E. Hooker, Terry Parks | 2018-07-10 |
| 9952875 | Microprocessor with ALU integrated into store unit | Gerard M. Col, Rodney E. Hooker | 2018-04-24 |
| 9915998 | Power saving mechanism to reduce load replays in out-of-order processor | Gerard M. Col, G. Glenn Henry | 2018-03-13 |
| 9910785 | Cache memory budgeted by ways based on memory access type | Rodney E. Hooker, Douglas R. Reed, John Michael Greer | 2018-03-06 |
| 9898418 | Processor including single invalidate page instruction | — | 2018-02-20 |