JC

Jasmeet S. Chawla

IN Intel: 3 patents #763 of 5,158Top 15%
📍 Hillsboro, OR: #65 of 454 inventorsTop 15%
🗺 Oregon: #625 of 4,132 inventorsTop 20%
Overall (2018): #72,783 of 503,207Top 15%
3
Patents 2018

Issued Patents 2018

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
10109583 Method for creating alternate hardmask cap interconnect structure with increased overlay margin Robert L. Bristol, Manish Chandhok, Florian Gstrein, Eungnak Han, Rami Hourani +3 more 2018-10-23
10032643 Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme Ruth A. Brain, Richard E. Schenker, Kanwal Jit Singh, Alan M. Myers 2018-07-24
9911694 Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches Christopher J. Jezewski 2018-03-06