Issued Patents 2018
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10141437 | Extreme high mobility CMOS logic | Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Justin K. Brask +3 more | 2018-11-27 |
| 10014377 | III-V field effect transistor on a dielectric layer | Cheng-Wei Cheng, Edward W. Kiewra, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun | 2018-07-03 |
| 9985113 | Fabrication process for mitigating external resistance of a multigate device | Anirban Basu, Guy M. Cohen | 2018-05-29 |
| 9941363 | III-V transistor device with self-aligned doped bottom barrier | Cheng-Wei Cheng, Pranita Kerber, Yanning Sun | 2018-04-10 |
| 9922830 | Hybrid III-V technology to support multiple supply voltages and off state currents on same chip | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2018-03-20 |
| 9882021 | Planar III-V field effect transistor (FET) on dielectric layer | Cheng-Wei Cheng, Edward W. Kiewra, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu +1 more | 2018-01-30 |
| 9865688 | Device isolation using preferential oxidation of the bulk substrate | Anirban Basu, Guy M. Cohen, Yu Zhu | 2018-01-09 |