Issued Patents 2018
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163864 | Vertically stacked wafers and methods of forming same | — | 2018-12-25 |
| 10153224 | Backside spacer structures for improved thermal performance | Rahul Agarwal, Haojun Zhang | 2018-12-11 |
| 10134647 | Methods for forming interconnect assemblies with probed bond pads | Owen R. Fay, Kyle K. Kirby, Jaspreet S. Gandhi | 2018-11-20 |
| 10090227 | Back biasing in SOI FET technology | Bartlomiej Jan Pawlak | 2018-10-02 |
| 10083958 | Deep trench metal-insulator-metal capacitors | Sukeshwar Kannan, Somnath Ghosh, Daniel M. Smith | 2018-09-25 |
| 10069490 | Method, apparatus and system for voltage compensation in a semiconductor wafer | Sukeshwar Kannan, Mehdi Sadi | 2018-09-04 |
| 10066303 | Thin NiB or CoB capping layer for non-noble metallic bonding landing pads | Eric Beyne, Joeri De Vos, Jaber Derakhshandeh, George Vakanas | 2018-09-04 |
| 10026883 | Wafer bond interconnect structures | Rahul Agarwal | 2018-07-17 |
| 9865570 | Integrated circuit package with thermally conductive pillar | Kathryn C. Rivera | 2018-01-09 |