Issued Patents 2018
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10114920 | Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic | Umesh Gupta, Shashank Tripathi, Naresh Kumar, Prashant Sethia, Ritika Govila | 2018-10-30 |
| 9881123 | Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact | Ratnakar Goyal, Manuj Verma, Igor Keller | 2018-01-30 |