Issued Patents 2018
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10114920 | Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic | Umesh Gupta, Naresh Kumar, Arvind Nembili Veeravalli, Prashant Sethia, Ritika Govila | 2018-10-30 |