MV

Manuj Verma

CS Cadence Design Systems: 2 patents #20 of 223Top 9%
📍 Sidhauli, IN: #1 of 43 inventorsTop 3%
Overall (2018): #121,145 of 503,207Top 25%
2
Patents 2018

Issued Patents 2018

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10031986 System and method for creating a spice deck for path-based analysis of an electronic circuit design using a stage-based technique Vishnu Kumar 2018-07-24
9881123 Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact Ratnakar Goyal, Igor Keller, Arvind Nembili Veeravalli 2018-01-30