Issued Patents 2018
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10128198 | Double side via last method for double embedded patterned substrate | You-Lung Yen, Chih-Cheng Lee | 2018-11-13 |
| 10096542 | Substrate, semiconductor package structure and manufacturing process | Chih-Cheng Lee | 2018-10-09 |
| 10083902 | Semiconductor package structure and semiconductor process | Chih-Cheng Lee, Cheng-Lin Ho | 2018-09-25 |
| 10079156 | Semiconductor package including dielectric layers defining via holes extending to component pads | Chih-Cheng Lee, Yu-Lin Shih, You-Lung Yen | 2018-09-18 |