Issued Patents 2018
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10128198 | Double side via last method for double embedded patterned substrate | Chih-Cheng Lee, Yuan-Chang Su | 2018-11-13 |
| 10079156 | Semiconductor package including dielectric layers defining via holes extending to component pads | Chih-Cheng Lee, Yuan-Chang Su, Yu-Lin Shih | 2018-09-18 |