Issued Patents 2017
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9698020 | CMOS Vt control integration by modification of metal-containing gate electrodes | Genji Nakamura | 2017-07-04 |
| 9607888 | Integration of ALD barrier layer and CVD Ru liner for void-free Cu filling | Kai-Hung Yu, Tadahiro Ishizaka, Manabu Oie, Fumitaka Amano, Steven P. Consiglio +3 more | 2017-03-28 |