Issued Patents 2017
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853155 | MOS devices having epitaxy regions with reduced facets | Chii-Horng Li, Kun-Mu Li, Tze-Liang Lee, Tsz-Mei Kwok | 2017-12-26 |
| 9842910 | Methods for manufacturing devices with source/drain structures | Tsz-Mei Kwok, Kuan-Yu Chen, Hsien-Hsin Lin | 2017-12-12 |
| 9806171 | Method for making source and drain regions of a MOSFET with embedded germanium-containing layers having different germanium concentration | Tsz-Mei Kwok, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee | 2017-10-31 |
| 9793404 | Silicon germanium p-channel FinFET stressor structure and method of making same | Liang Chen | 2017-10-17 |
| 9768302 | Semiconductor structure and fabricating method thereof | Chih-Chiang Chang, Kun-Mu Li | 2017-09-19 |
| 9755077 | Source and drain stressors with recessed top surfaces | Kun-Mu Li, Tsz-Mei Kwok, Chii-Horng Li, Tze-Liang Lee | 2017-09-05 |
| 9698243 | Transistor strain-inducing scheme | Tsz-Mei Kwok, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee | 2017-07-04 |
| 9691898 | Germanium profile for channel strain | Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2017-06-27 |
| 9666691 | Epitaxy profile engineering for FinFETs | Chien-Chang Su, Tsz-Mei Kwok, Hsien-Hsin Lin, Yi-Fang Pai, Kuan-Yu Chen | 2017-05-30 |
| 9666686 | MOS devices having epitaxy regions with reduced facets | Chii-Horng Li, Kun-Mu Li, Tze-Liang Lee, Tsz-Mei Kwok | 2017-05-30 |
| 9601619 | MOS devices with non-uniform P-type impurity profile | Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2017-03-21 |
| 9583483 | Source and drain stressors with recessed top surfaces | Kun-Mu Li, Tsz-Mei Kwok, Chii-Horng Li, Tze-Liang Lee | 2017-02-28 |