Issued Patents 2017
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9812251 | Varainductor and operation method thereof based on mutual capacitance | Yi-Hsuan Liu, Hsieh-Hung Hsieh, Chewn-Pu Jou | 2017-11-07 |
| 9807867 | Interconnect structure and method of manufacturing the same | Jiun Yi Wu, Chien-Hsun Lee, Chewn-Pu Jou | 2017-10-31 |
| 9800154 | Voltage supply unit and method for operating the same | Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang | 2017-10-24 |
| 9786976 | Transmission line design and method, where high-k dielectric surrounds the transmission line for increased isolation | Jiun Yi Wu, Chien-Hsun Lee, Chewn-Pu Jou | 2017-10-10 |
| 9761553 | Inductor with conductive trace | Chewn-Pu Jou, Chuei-Tang Wang | 2017-09-12 |
| 9712145 | Delay line circuit with variable delay line unit | Ming-Chieh Huang, Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin | 2017-07-18 |
| 9698146 | Multi-gate and complementary varactors in FinFET process | Chi-Hsien Lin, Ying-Ta Lu, Hsien-Yuan Liao, Ho-Hsiang Chen, Chewn-Pu Jou | 2017-07-04 |
| 9628102 | Integrated circuits, liquid crystal display (LCD) drivers, and systems | Nang-Ping Tu, Mingo Liu, I-Fey Wang | 2017-04-18 |
| 9607121 | Cascode CMOS structure | Chih-Ping Chao, Chewn-Pu Jou, Yung-Chow Peng, Harry-Hak-Lay Chuang, Kuo-Tung Sung | 2017-03-28 |
| 9559686 | Input/output circuit | Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang | 2017-01-31 |
| 9548267 | Three dimensional circuit including shielded inductor and method of forming same | Ming-Hsien Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Chewn-Pu Jou, Sa-Lly Liu | 2017-01-17 |