Issued Patents 2017
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9831173 | Slot-shielded coplanar strip-line compatible with CMOS processes | Yu-Ling Lin, Hsiao-Tsung Yen, Ho-Hsiang Chen, Chewn-Pu Jou | 2017-11-28 |
| 9658275 | De-embedding on-wafer devices | Hsiao-Tsung Yen, Ho-Hsiang Chen, Sa-Lly Liu, Yu-Ling Lin | 2017-05-23 |
| 9653531 | Methods of manufacturing a package | Hsiao-Tsung Yen, Min-Chie Jeng, Hsien-Pin Hu, Tzuan-Horng Liu, Chung-Yu Lu +1 more | 2017-05-16 |
| 9633940 | Structure and method for a high-K transformer with capacitive coupling | Hsiao-Tsung Yen, Ho-Hsiang Chen, Min-Chie Jeng, Yu-Ling Lin | 2017-04-25 |
| 9633149 | System and method for modeling through silicon via | Hsiao-Tsung Yen, Yu-Ling Lin | 2017-04-25 |
| 9607942 | Semiconductor device with patterned ground shielding | Hsiao-Tsung Yen, Cheng-Wei Luo, Kung-Hao Liang | 2017-03-28 |
| 9559053 | Compact vertical inductors extending in vertical planes | Hsiao-Tsung Yen, Huan-Neng Chen, Yu-Ling Lin, Mei-Show Chen, Ho-Hsiang Chen +1 more | 2017-01-31 |