Issued Patents 2017
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853112 | Device and method to connect gate regions separated using a gate cut | Yanxiang Liu, Kern Rim | 2017-12-26 |
| 9824936 | Adjacent device isolation | Vladimir Machkaoutsan, Mustafa Badaroglu, Jeffrey Junhao Xu, Choh Fei Yeap | 2017-11-21 |
| 9812188 | Static random-access memory (SRAM) sensor for bias temperature instability | Niladri Narayan Mojumder, Zhongze Wang, Xiaonan Chen, Choh Fei Yeap | 2017-11-07 |
| 9806083 | Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance, and related methods | Niladri Narayan Mojumder, Zhongze Wang, Kern Rim, Choh Fei Yeap | 2017-10-31 |
| 9799560 | Self-aligned structure | Jeffrey Junhao Xu, Kern Rim, Da Yang, John Jianhong Zhu, Junjing Bao +4 more | 2017-10-24 |
| 9793164 | Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices | Vladimir Machkaoutsan, John Jianhong Zhu, Junjing Bao, Jeffrey Junhao Xu, Mustafa Badaroglu +2 more | 2017-10-17 |
| 9721891 | Integrated circuit devices and methods | Jeffrey Junhao Xu, Junjing Bao, John Jianhong Zhu, Niladri Narayan Mojumder, Choh Fei Yeap | 2017-08-01 |
| 9698232 | Conductive cap for metal-gate transistor | Haining Yang | 2017-07-04 |
| 9698267 | Fin-type device system and method | Mohamed H. Abu-Rahma, Beom-Mo Han | 2017-07-04 |
| 9691868 | Merging lithography processes for gate patterning | Zhongze Wang, Choh Fei Yeap | 2017-06-27 |
| 9666481 | Reduced height M1 metal lines for local on-chip routing | Choh Fei Yeap, Zhongze Wang, Niladri Narayan Mojumder, Mustafa Badaroglu | 2017-05-30 |
| 9660649 | Voltage scaling for holistic energy management | Niladri Narayan Mojumder, Kern Rim, Choh Fei Yeap | 2017-05-23 |
| 9653399 | Middle-of-line integration methods and semiconductor devices | John Jianhong Zhu, Da Yang, Jeffrey Junhao Xu, Kern Rim | 2017-05-16 |
| 9620454 | Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods | John Jianhong Zhu, Kern Rim, Jeffrey Junhao Xu, Da Yang | 2017-04-11 |
| 9607988 | Off-center gate cut | Yanxiang Liu | 2017-03-28 |
| 9594864 | Method for asymmetrical geometrical scaling | Choh Fei Yeap | 2017-03-14 |
| 9564361 | Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device | Choh Fei Yeap, Zhongze Wang, John Jianhong Zhu | 2017-02-07 |
| 9564518 | Method and apparatus for source-drain junction formation in a FinFET with in-situ doping | Vladimir Machkaoutsan, Jeffrey Junhao Xu, Mustafa Badaroglu, Choh Fei Yeap | 2017-02-07 |
| 9542518 | User experience based management technique for mobile system-on-chips | Niladri Narayan Mojumder, Kern Rim, Choh Fei Yeap | 2017-01-10 |
| 9543248 | Integrated circuit devices and methods | Jeffrey Junhao Xu, Junjing Bao, John Jianhong Zhu, Niladri Narayan Mojumder, Choh Fei Yeap | 2017-01-10 |
| 9536596 | Three-port bit cell having increased width | Niladri Narayan Mojumder, Zhongze Wang, Choh Fei Yeap | 2017-01-03 |