Issued Patents 2017
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9720040 | Timing-aware test generation and fault simulation | Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski | 2017-08-01 |
| 9568552 | Logic built-in self-test with high test coverage and low switching activity | Janusz Rajski | 2017-02-14 |