Issued Patents 2017
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9728499 | Set of stepped surfaces formation for a multilevel interconnect structure | Seiji Shimabukuro, Hiroaki Iuchi, Naoki Takeguchi | 2017-08-08 |
| 9673304 | Methods and apparatus for vertical bit line structures in three-dimensional nonvolatile memory | Akira Nakada, Tetsuya Yamada, Manabu Hayashi, Takashi Matsubara, Sung-Tae Lee +1 more | 2017-06-06 |
| 9666799 | Concave word line and convex interlayer dielectric for protecting a read/write layer | Naohito Yanagida, Cheng Feng, Akira Nakada, Steven J. Radigan, Eiji Hayashi | 2017-05-30 |
| 9620712 | Concave word line and convex interlayer dielectric for protecting a read/write layer | Eiji Hayashi, Naohito Yanagida, Akira Nakada | 2017-04-11 |
| 9601502 | Multiheight contact via structures for a multilevel interconnect structure | Keisuke Izumi | 2017-03-21 |
| 9576967 | Method of suppressing epitaxial growth in support openings and three-dimensional memory device containing non-epitaxial support pillars in the support openings | Hajime Kimura, Seiji Shimabukuro, Shuji Minagawa, Masanori Tsutsumi | 2017-02-21 |