Issued Patents 2017
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9805790 | Memory cell with retention using resistive memory | Nathaniel J. August, Pulkit Jain, Stefan Rusu, Fatih Hamzaoglu, Rangharajan Venkatesan +4 more | 2017-10-31 |
| 9766827 | Apparatus for data retention and supply noise mitigation using clamps | Pascal A. Meinerzhagen, Stephen Kim, Anupama A. Thaploo | 2017-09-19 |
| 9755631 | Apparatus and method for reducing di/dt during power wake-up | Yong Shim, Jaydeep P. Kulkarni, Pascal A. Meinerzhagen | 2017-09-05 |
| 9734880 | Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctions | Charles Augustine, Somnath Paul, Sadique Ul Ameen Sheik | 2017-08-15 |
| 9685208 | Assist circuit for memory | Jaydeep P. Kulkarni, Anupama A. Thaploo, Iqbal Rajwani, Kyung Hoae Koo, Eric A. Karl | 2017-06-20 |
| 9680472 | Voltage level shifter circuit | Amit R. Trivedi, Jaydeep P. Kulkarni, Carlos Tokunaga, James W. Tschanz | 2017-06-13 |
| 9678878 | Disabling cache portions during low voltage operations | Christopher B. Wilkerson, Vivek K. De, Ming Zhang, Jaume Abella, Javier Carretero Casado +3 more | 2017-06-13 |
| 9666268 | Apparatus for adjusting supply level to improve write margin of a memory cell | Yih Wang, Fatih Hamzaoglu | 2017-05-30 |
| 9665144 | Methods and systems for energy efficiency and energy conservation including entry and exit latency reduction for low power states | Jawad Nasrullah, Kelvin Kwan, Jaydeep P. Kulkarni | 2017-05-30 |
| 9627039 | Apparatus for reducing write minimum supply voltage for memory | Jaydeep P. Kulkarni, James W. Tschanz, Bibiche M. Geuskens, Vivek K. De | 2017-04-18 |
| 9621163 | Current steering level shifter | Amit R. Trivedi, Jaydeep P. Kulkarni, Dinesh Somasekhar, Carlos Tokunaga, James W. Tschanz | 2017-04-11 |
| 9563263 | Graphics processor sub-domain voltage regulation | Subramaniam Maiyuran, James W. Tschanz | 2017-02-07 |