Issued Patents 2017
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9831175 | Method, apparatus, and system for E-fuse in advanced CMOS technologies | Min-hwa Chi | 2017-11-28 |
| 9831123 | Methods of forming MIS contact structures on transistor devices | Zhiguo Sun, Keith H. Tabakman | 2017-11-28 |
| 9812393 | Programmable via devices with metal/semiconductor via links and fabrication methods thereof | Ajey Poovannummoottil Jacob, Min-hwa Chi | 2017-11-07 |
| 9754903 | Semiconductor structure with anti-efuse device | Min-hwa Chi, Ajey Poovannummoottil Jacob | 2017-09-05 |
| 9754843 | Heterogeneous integration of 3D Si and III-V vertical nanowire structures for mixed signal circuits fabrication | Ajey Poovannummoottil Jacob | 2017-09-05 |
| 9698241 | Integrated circuits with replacement metal gates and methods for fabricating the same | Min-hwa Chi, Mitsuhiro Togo | 2017-07-04 |
| 9691497 | Programmable devices with current-facilitated migration and fabrication methods | Min-hwa Chi, Ajey Poovannummoottil Jacob | 2017-06-27 |
| 9659862 | Method, apparatus, and system for e-fuse in advanced CMOS technologies | Min-hwa Chi | 2017-05-23 |
| 9620381 | Facilitating etch processing of a thin film via partial implantation thereof | Huy Cao, Hui Zhan, Huang Liu | 2017-04-11 |
| 9613855 | Methods of forming MIS contact structures on transistor devices in CMOS applications | Zhiguo Sun, Keith H. Tabakman | 2017-04-04 |
| 9588044 | Inline buried metal void detection by surface plasmon resonance (SPR) | Sabarinath Jayaseelan | 2017-03-07 |
| 9570572 | Multiple layer interface formation for semiconductor structure | Min-hwa Chi | 2017-02-14 |
| 9564447 | Methods for fabricating programmable devices and related structures | Ajey Poovannummoottil Jacob, Min-hwa Chi | 2017-02-07 |