PS

Prashant Sethia

CS Cadence Design Systems: 2 patents #21 of 238Top 9%
Overall (2017): #115,024 of 506,227Top 25%
2
Patents 2017

Issued Patents 2017

Patent #TitleCo-InventorsDate
9633159 Method and system for performing distributed timing signoff and optimization Vipul Parikh, Lalit Bharat, Shagufta Siddique, Naresh Kumar 2017-04-25
9589096 Method and apparatus for integrating spice-based timing using sign-off path-based analysis Umesh Gupta, Vishnu Kumar, Manish Bansal, Naresh Kumar, Manuj Verma 2017-03-07