VP

Vipul Parikh

CS Cadence Design Systems: 1 patents #55 of 238Top 25%
Overall (2017): #204,184 of 506,227Top 45%
1
Patents 2017

Issued Patents 2017

Patent #TitleCo-InventorsDate
9633159 Method and system for performing distributed timing signoff and optimization Lalit Bharat, Shagufta Siddique, Prashant Sethia, Naresh Kumar 2017-04-25