Issued Patents 2017
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9851777 | Power gating based on cache dirtiness | Manish Arora, Yasuko Eckert, Nuwan Jayasena, Srilatha Manne, Madhu Saravana Sibi Govindan +1 more | 2017-12-26 |
| 9658663 | Thermally-aware throttling in a three-dimensional processor stack | Wei Huang, Manish Arora, Yasuko Eckert | 2017-05-23 |
| 9619290 | Hardware and runtime coordinated load balancing for parallel applications | Peter Bailey, Manish Arora | 2017-04-11 |