Issued Patents 2017
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9851777 | Power gating based on cache dirtiness | Manish Arora, Indrani Paul, Nuwan Jayasena, Srilatha Manne, Madhu Saravana Sibi Govindan +1 more | 2017-12-26 |
| 9818455 | Query operations for stacked-die memory device | Gabriel H. Loh, Nuwan Jayasena, James M. O'Connor | 2017-11-14 |
| 9766936 | Selecting a resource from a set of resources for performing an operation | Bradford M. Beckmann, Mithuna S. Thottethodi, James M. O'Connor, Mauricio Breternitz, Lisa R. Hsu +1 more | 2017-09-19 |
| 9746908 | Pruning of low power state information for a processor | Derek Robert Hower, Marc S. Orr | 2017-08-29 |
| 9734059 | Methods and apparatus for data cache way prediction based on classification as stack data | Lena E. Olson, Vilas Sridharan, James M. O'Connor, Mark D. Hill, Srilatha Manne | 2017-08-15 |
| 9710392 | Virtual memory mapping for improved DRAM page locality | Syed Ali Jafri, Srilatha Manne, Mithuna S. Thottethodi | 2017-07-18 |
| 9672161 | Configuring a cache management mechanism based on future accesses in a cache | Gabriel H. Loh | 2017-06-06 |
| 9658663 | Thermally-aware throttling in a three-dimensional processor stack | Wei Huang, Manish Arora, Indrani Paul | 2017-05-23 |