Issued Patents 2016
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9383767 | Circuit design for balanced logic stress | Nathaniel R. Chadwick, Frances S. M. Clougherty, Kirk D. Peterson, Mack W. Riley | 2016-07-05 |
| 9310827 | Multiple active vertically aligned cores for three-dimensional chip stack | Gerald K. Bartley, Darryl J. Becker | 2016-04-12 |
| 9312199 | Intelligent chip placement within a three-dimensional chip stack | Gerald K. Bartley, Darryl J. Becker, Philip Raymond Germann | 2016-04-12 |
| 9281261 | Intelligent chip placement within a three-dimensional chip stack | Gerald K. Bartley, Darryl J. Becker, Philip Raymond Germann | 2016-03-08 |
| 9250645 | Circuit design for balanced logic stress | Nathaniel R. Chadwick, Frances S. M. Clougherty, Kirk D. Peterson, Mack W. Riley | 2016-02-02 |