Issued Patents 2016
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9513565 | Using wafer geometry to improve scanner correction effectiveness for overlay control | Craig MacNaughton, Sathish Veeraraghavan, Jaydeep Sinha, Amir Azordegan | 2016-12-06 |
| 9430593 | System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking | Sathish Veeraraghavan, Jaydeep Sinha, Haiguang Chen, Michael D. Kirk | 2016-08-30 |
| 9373165 | Enhanced patterned wafer geometry measurements based design improvements for optimal integrated chip fabrication performance | Amir Azordegan, Craig MacNaughton, Jaydeep Sinha | 2016-06-21 |
| 9354526 | Overlay and semiconductor process control using a wafer geometry metric | Sathish Veeraraghavan, Jaydeep Sinha | 2016-05-31 |