Issued Patents 2016
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9484205 | Semiconductor device having self-aligned gate contacts | Josephine B. Chang, Michael A. Guillorn | 2016-11-01 |
| 9455195 | Method of forming performance optimized gate structures by silicidizing lowered source and drain regions | Katsunori Onishi, Jian-Shen Yu | 2016-09-27 |
| 9443951 | Embedded planar source/drain stressors for a finFET including a plurality of fins | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2016-09-13 |
| 9406745 | Method of manufacturing super junction for semiconductor device | Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao | 2016-08-02 |
| 9379180 | Super junction for semiconductor device and method for manufacturing the same | Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao | 2016-06-28 |
| 9287399 | Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels | Bhupesh Chandra, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar +6 more | 2016-03-15 |