Issued Patents 2016
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9503091 | Wordline decoder circuits for embedded charge trap multi-time-programmable-read-only-memory | Derek H. Leu, Ming Yin | 2016-11-22 |
| 9497027 | Encryption engine with twin cell memory array | Xiang Chen, Derek H. Leu, Sami Rosenblatt | 2016-11-15 |
| 9460760 | Data-dependent self-biased differential sense amplifier | Balaji Jayaraman, Thejas Kempanna, Ramesh Raghavan, Krishnan S. Rengarajan, Rajesh Reddy Tummuru | 2016-10-04 |
| 9436845 | Physically unclonable fuse using a NOR type memory array | Subramanian S. Iyer, Chandrasekharan Kothandaraman, Derek H. Leu, Sami Rosenblatt | 2016-09-06 |
| 9431339 | Wiring structure for trench fuse component with methods of fabrication | Edward P. Maciejewski, Subramanian S. Iyer, Chengwen Pei, Deepal Wehella-Gamage | 2016-08-30 |
| 9431340 | Wiring structure for trench fuse component with methods of fabrication | Edward P. Maciejewski, Subramanian S. Iyer, Chengwen Pei, Deepal Wehella-Gamage | 2016-08-30 |
| 9424308 | Hierarchical in-memory sort engine | Alper Buyuktosunoglu, Srivatsan Chellappa, Karthik V. Swaminathan | 2016-08-23 |
| 9418745 | Rebalancing in twin cell memory schemes to enable multiple writes | Xiang Chen, Derek H. Leu, Dan Moy | 2016-08-16 |
| 9396143 | Hierarchical in-memory sort engine | Alper Buyuktosunoglu, Srivatsan Chellappa, Karthik V. Swaminathan | 2016-07-19 |
| 9355739 | Bitline circuits for embedded charge trap multi-time-programmable-read-only-memory | Pamela Castalino, Derek H. Leu | 2016-05-31 |
| 9324430 | Method for defining a default state of a charge trap based memory cell | Sheikh Sabiq Chishti, Krishnan S. Rengarajan, Deepal Wehella-Gamage | 2016-04-26 |
| 9268863 | Hierarchical in-memory sort engine | Alper Buyuktosunoglu, Srivatsan Chellappa, Karthik V. Swaminathan | 2016-02-23 |