Issued Patents 2016
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9507646 | Cycle-level thread alignment on multi-threaded processors | Ramon Bertran, Pradip Bose, Timothy Siegel | 2016-11-29 |
| 9471535 | 3-D stacked multiprocessor structures and methods for multimodal operation of same | Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan K. Kailas | 2016-10-18 |
| 9471136 | Predictively turning off a charge pump supplying voltage for overdriving gates of the power switch header in a microprocessor with power gating | Pradip Bose, Hans M. Jacobson, Victor Zyuban | 2016-10-18 |
| 9442884 | 3-D stacked multiprocessor structures and methods for multimodal operation of same | Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan K. Kailas | 2016-09-13 |
| 9431084 | Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM) | Pradip Bose, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers, Vijayalakshmi Srinivasan | 2016-08-30 |
| 9423859 | Delaying execution in a processor to increase power savings | Pradip Bose, Hans M. Jacobson, Augusto J. Vega | 2016-08-23 |
| 9424308 | Hierarchical in-memory sort engine | Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan | 2016-08-23 |
| 9423865 | Accelerating microprocessor core wake up via charge from capacitance tank without introducing noise on power grid of running microprocessor cores | Pradip Bose, Hans M. Jacobson, Victor Zyuban | 2016-08-23 |
| 9418721 | Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM) | Pradip Bose, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers, Vijayalakshmi Srinivasan | 2016-08-16 |
| 9406368 | Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM) | Pradip Bose, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers, Vijayalakshmi Srinivasan | 2016-08-02 |
| 9396143 | Hierarchical in-memory sort engine | Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan | 2016-07-19 |
| 9389674 | Predictively turning off a charge pump supplying voltage for overdriving gates of the power switch header in a microprocessor with power gating | Pradip Bose, Hans M. Jacobson, Victor Zyuban | 2016-07-12 |
| 9389675 | Power management for in-memory computer systems | Pradip Bose, Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair +1 more | 2016-07-12 |
| 9389876 | Three-dimensional processing system having independent calibration and statistical collection layer | Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan K. Kailas | 2016-07-12 |
| 9383411 | Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers | Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan K. Kailas | 2016-07-05 |
| 9372519 | Dynamic power distribution | Pradip Bose, Hans M. Jacobson | 2016-06-21 |
| 9361175 | Dynamic detection of resource management anomalies in a processing system | Pradip Bose, Augusto J. Vega | 2016-06-07 |
| 9354943 | Power management for multi-core processing systems | Pradip Bose, Michael Stephen Floyd, Heather L. Hanson, Hans M. Jacobson, Karthick Rajamani +3 more | 2016-05-31 |
| 9351899 | Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM) | Pradip Bose, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers, Vijayalakshmi Srinivasan | 2016-05-31 |
| 9336144 | Three-dimensional processing system having multiple caches that can be partitioned, conjoined, and managed according to more than one set of rules and/or configurations | Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan K. Kailas | 2016-05-10 |
| 9323302 | Rotating voltage control | Pradip Bose, Hans M. Jacobson, Victor Zyuban | 2016-04-26 |
| 9298253 | Accelerating the microprocessor core wakeup by predictively executing a subset of the power-up sequence | Pradip Bose, Hans M. Jacobson, Victor Zyuban | 2016-03-29 |
| 9298672 | 3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components | Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan K. Kailas | 2016-03-29 |
| 9298466 | Multi-threaded processor instruction balancing through instruction uncertainty | Brian R. Prasky, Vijayalakshmi Srinivasan | 2016-03-29 |
| 9298234 | Dynamic power distribution | Pradip Bose, Hans M. Jacobson | 2016-03-29 |