Issued Patents 2016
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9529962 | System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design | Amit Dhuria, Pradeep Yadav, Manuj Verma, Prashant Sethia | 2016-12-27 |
| 9405882 | High performance static timing analysis system and method for input/output interfaces | Amit Dhuria, Prashant Sethia, Jeannette Sutherland, Shashank Tripathi | 2016-08-02 |