Issued Patents 2016
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9529962 | System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design | Amit Dhuria, Manuj Verma, Naresh Kumar, Prashant Sethia | 2016-12-27 |
| 9384310 | View data sharing for efficient multi-mode multi-corner timing analysis | Igor Keller, Jijun Chen | 2016-07-05 |