Issued Patents 2016
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9529962 | System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design | Amit Dhuria, Pradeep Yadav, Naresh Kumar, Prashant Sethia | 2016-12-27 |