Issued Patents 2011
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8067792 | Memory device with memory cell including MuGFET and FIN capacitor | Weize Xiong, Cloves Rinn Cleavelin, Howard L. Tigelaar | 2011-11-29 |
| 8058161 | Recessed STI for wide transistors | Gabriel G. Barna, Brian K. Kirkpatrick | 2011-11-15 |
| 8049214 | Degradation correction for finFET circuits | — | 2011-11-01 |
| 8018780 | Temperature dependent back-bias for a memory array | Theodore W. Houston | 2011-09-13 |
| 7978004 | Body bias coordinator, method of coordinating a body bias and sub-circuit power supply employing the same | Theodore W. Houston | 2011-07-12 |
| 7974595 | Methodology for assessing degradation due to radio frequency excitation of transistors | Vijay Reddy, Siraj Akhtar, Srikanth Krishnan, Karan Singh Bhatia | 2011-07-05 |
| 7960760 | Electrically programmable fuse | — | 2011-06-14 |
| 7952378 | Tunable stress technique for reliability degradation measurement | Vijay Reddy | 2011-05-31 |
| 7907456 | Memory having circuitry controlling the voltage differential between the word line and array supply voltage | Theodore W. Houston | 2011-03-15 |
| 7893723 | Minimizing leakage in logic designs | — | 2011-02-22 |
| 7888192 | Process for forming integrated circuits with both split gate and common gate FinFET transistors | Theodore W. Houston | 2011-02-15 |