Issued Patents 2011
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8039338 | Method for reducing defects of gate of CMOS devices during cleaning processes by modifying a parasitic PN junction | Manfred Horstmann, Karsten Wieczorek, Kerstin Ruttloff | 2011-10-18 |
| 8003460 | Method of forming a semiconductor structure comprising a formation of at least one sidewall spacer structure | Frank Wirbeleit, Rolf Stephan | 2011-08-23 |
| 7897451 | Method for creating tensile strain by selectively applying stress memorization techniques to NMOS transistors | Maciej Wiatr, Casey Scott, Andreas Gehring, Andy Wei | 2011-03-01 |