Issued Patents 2011
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8003486 | Method of making a semiconductor device having a strained semiconductor active region using edge relaxation, a buried stressor layer and a sacrificial stressor layer | R. Stockton Gaines, Paul A. Clifton | 2011-08-23 |
| 7972916 | Method of forming a field effect transistors with a sacrificial stressor layer and strained source and drain regions formed in recesses | Paul A. Clifton, R. Stockton Gaines | 2011-07-05 |
| 7902029 | Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor | Daniel E. Grupp, Paul A. Clifton, Carl M. Faulkner | 2011-03-08 |
| 7883980 | Insulated gate field effect transistor having passivated schottky barriers to the channel | Daniel E. Grupp | 2011-02-08 |
| 7884003 | Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions | Daniel E. Grupp | 2011-02-08 |