Issued Patents 2005
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6977519 | Digital logic with reduced leakage | Suhwan Kim, Daniel R. Knebel, Stephen V. Kosonocky | 2005-12-20 |
| 6975532 | Quasi-static random access memory | Stephen V. Kosonocky | 2005-12-13 |
| 6920061 | Loadless NMOS four transistor dynamic dual Vt SRAM cell | Rajiv V. Joshi, Stephen V. Kosonocky | 2005-07-19 |
| 6876595 | Decode path gated low active power SRAM | Stephen V. Kosonocky | 2005-04-05 |
| 6861739 | Minimum metal consumption power distribution network on a bonded die | Ashok K. Kapoor | 2005-03-01 |
| 6839299 | Method and structure for reducing gate leakage and threshold voltage fluctuation in memory cells | Stephen V. Kosonocky | 2005-01-04 |