Issued Patents 2005
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6977519 | Digital logic with reduced leakage | Azeez Bhavnagarwala, Suhwan Kim, Daniel R. Knebel | 2005-12-20 |
| 6975532 | Quasi-static random access memory | Azeez Bhavnagarwala | 2005-12-13 |
| 6920061 | Loadless NMOS four transistor dynamic dual Vt SRAM cell | Azeez Bhavnagarwala, Rajiv V. Joshi | 2005-07-19 |
| 6917221 | Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits | Kerry Bernstein, Randy W. Mann, Jeffrey H. Oppold | 2005-07-12 |
| 6891419 | Methods and apparatus for employing feedback body control in cross-coupled inverters | Paul D. Kartschoke, Randy W. Mann, Norman J. Rohrer | 2005-05-10 |
| 6876595 | Decode path gated low active power SRAM | Azeez Bhavnagarwala | 2005-04-05 |
| 6876252 | Non-abrupt switching of sleep transistor of power gate structure | Suhwan Kim, Daniel R. Knebel | 2005-04-05 |
| 6839299 | Method and structure for reducing gate leakage and threshold voltage fluctuation in memory cells | Azeez Bhavnagarwala | 2005-01-04 |